The present invention relates to an input and output buffer circuit and, in particular, relates to an input and output buffer circuit through which other circuits and LSIs each operating at different voltage levels are permitted to be connected to each other.
LSIs and VLSIs constituted by Metal Oxide Film Semiconductors (MOSs) are being developed with a view toward a higher integration through micronization thereof and the use of a lower voltage power source; however, the application of systems using these LSIs and VLSIs is not limited to a system which closes with only a single lower voltage source. Therefore, there still remains a demand for an input and output buffer circuit through which LSIs, each operating at different voltage levels, are permitted to be connected to each other. Thus, an input and output buffer circuit which meets the requirements for a hybrid system operating at different voltage levels and which includes some of the counter measures therefor has been proposed.
An example of such input and output buffer circuits is disclosed in a paper by Tetsuhiro Nishihara et al. "IBM moves to sell LSIs to outside customers, and discloses gate-array technology, a core technology which is to be employed for note type personal computer operating at 3V power source" (NIKKEI MICRODEVICES, October, 1992, pp. 83-88), and a circuit disclosed therein is illustrated in FIG. 16.
The structure and the operation of the circuit shown in FIG. 16 will be explained. In FIG. 16, Q1 and Q2 form an input and output control circuit which is constituted by a two input NAND circuit, a two input NOR circuit and an inverter, and is controlled by an output enable signal OE and a data output signal DOUT. QP3 and QN3 are respectively driver PWMOS and NMOS transistors which constitute an output driver unit; while, Q3 is an input buffer, and DN1 and DP1 operate respectively as electrostatic destruction countermeasuring devices, with DN1 being a junction type diode and DP1 being a punch through type diode. The present input and output buffer circuit is designed to be operated at a power source voltage of Vcc1 (3.3V).
A first problem in conventional input and output buffer circuits occurs during the input mode thereof and when a high level voltage signal of 5.0V from another input and output buffer circuit, which is designed to be operated at a higher power source voltage of 5.0V, is directly applied to a PAD for an input and output buffer circuit, which is designed to be operated at a lower power source voltage of 3.3V. Namely, through a parasitic diode formed between the N well node NW, serving also as the substrate of the driver PMOS transistor QP3, and the source thereof, a current path is formed because of the potential difference between the PAD at 5.0V and Vcc1 (3.3V). In the FIG. 16 circuit, as a counter-measure for this problem, a PMOS transistor QP4 is turned off when a higher level signal potential of 5.0V is applied to the PAD terminal, and the potential of the N well node NW of the driver PMOS transistor QP3 is caused to float to prevent formation of the current path.
A second problem in the conventional input and output buffer circuits during the input mode is due to the fact that, because the potentials of 3.3V and 5.0V are respectively applied to the gate and the source connected to the PAD of the driver PMOS transistor QP3, the driver PMOS transistor QP3 cannot be turned off, thereby creating a current path therethrough. In the FIG. 16 circuit, a PMOS transistor QP2 is introduced which is designed to turn on when a high level potential signal of 5.0V is applied to the PAD, whereby the potential of the gate of the QP3 is made equal to the PAD potential of 5.0V connected to the source of the QP3 to avoid the formation of the current path.
Further, in order to prevent the potential of 5.0V at the gate of the QP3 from being applied to the output side of the two input NAND circuit Q1 via the newly introduced PMOS transistor QP2, a NMOS transistor QN1 is further provided. Still further, in order to prevent the potential at the gate of the PMOS transistor QP3 from dropping to Vcc1-V.sub.thQN1 (wherein V.sub.thQN1 is the threshold voltage of the NMOS transistor QN1) when the two input NAND circuit Q1 outputs the signal of high potential level of 3.3V, because of the provision of the NMOS transistor QN1, a transfer gate connected to PMOS transistor QP1 is further provided which is connected in parallel with the NMOS transistor QN1.
A third problem in the conventional input and output buffer circuits results because a PN junction type diode serving as an electrostatic destruction protecting device at the power source side is connected to Vcc1 (3.3V) at the cathode thereof, so that a current path is also formed due to the potential difference with the high potential level of 5.0V at the PAD. In the FIG. 16 circuit, as a counter-measure to this problem, formation of a current path is prevented through introduction of the punch-through type diode DP1.
A fourth problem in the conventional input and output buffer circuits is due to the fact that the signal of high potential level of 5.0V appearing at the PAD during the input mode thereof is also applied to the drain of the driver NMOS transistor QN3. In the FIG. 16 circuit, this problem is solved through the provision of a NMOS transistor QN2 which drops the potential applied to the driver NMOS transistor QN3 down to 3.3V-V.sub.thQN2 (wherein V.sub.thQN2 is the threshold voltage of the NMOS transistor QN2) to ensure protection for the QN3 against an excess voltage application.
A fifth problem in the conventional input and output buffer circuits is due to the fact that the signal of high potential level of 5.0V appearing at the PAD during the input mode thereof is also applied to the gate of the input buffer Q3. In the FIG. 16 circuit, this problem is solved through the provision of a NMOS transistor QN4 which drops the potential applied to the gate of the input buffer Q3 down to 3.3V-V.sub.thQN4 (wherein V.sub.thQN4 is the threshold voltage of the NMOS transistor QN4) to ensure protection for the input buffer Q3 against an excess voltage application.
In the FIG. 16 circuit, the potential of the N well node serving as the substrate of the driver PMOS transistor QP3 is determined by the PMOS transistor QP4. Namely, when the potential at the PAD terminal is less than Vcc1-V.sub.thQP4, the PMOS transistor QP4 is turned on and the potential of the N well node NW is fixed at Vcc1=3.3V, and when the potential of the PAD terminal is other than the above, for example, is larger than Vcc1-V.sub.thQP4, the PMOS transistor QP4 is turned off and the potential of the N well node is set to a floating level.
Another example of such input and output buffer circuits, which is disclosed in JP-A-4-329024(1992), is illustrated in FIG. 17. Only those countermeasures which are different from those of the FIG. 16 circuit for solving the problems in the conventional input and output buffer circuits through which other circuits, each operating at different power source voltage levels, are permitted to be connected to each other, will be explained. The N well node NW, serving as the substrate of the driver PMOS transistor receives the maximum potential of Vcc2=5.0V at the PAD terminal to cancel out the potential difference between the N well node NW and the drain of the driver PMOS transistor QP3 connected to the PAD terminal, so as to thereby avoid the formation of a current path. The FIG. 17 circuit uses two power sources of different voltage levels. Further, when the driver PMOS transistor QP3 is turned on, a voltage of 5.0V is applied between the gate and the N well node NW of the PMOS transistor QP3, which necessitates an increase in the withstanding voltage therebetween, such as by thickening the gate oxide film therein.
Still another example of such input and output buffer circuits, as disclosed in JP-A-5-227010(1993), which corresponds to U.S. Pat. No. 5,160,855, is illustrated in FIG. 18. The gate potential control by the voltage floating gate (VFG) circuit in FIG. 18 is equivalent to that shown in the FIG. 16 circuit, which makes the gate potential of the driver PMOS transistor QP3 equal to the source potential thereof connected to the PAD when the PAD receives the potential of 5.0V, so as to prevent the generation of a potential difference between the gate and the source thereof, prevent the turning on thereof and prevent the formation of a current path therethrough. Further, the potential control of the N well node NW serving as the substrate of the PMOS transistor QP3 is performed by a voltage floating well (VFW) circuit constituted by four PMOS transistors QP45, QP46, QP55 and QP56. The VFW circuit operates in such a manner that, when the PAD terminal potential.gtoreq.Vcc1+V.sub.thQP3, the PMOS transistor QP55 is turned on, the other PMOS transistors QP45, QP46 and QP56 are turned off and the potential of the N well node NW is made equal to the potential at the PAD terminal; when the PAD terminal potential.ltoreq.Vcc1-V.sub.thQP3, the PMOS transistor QP45 is turned on and the other PMOS transistors QP55, QP56 and QP46 are turned off and the potential of the N well node NW is rendered to Vcc1 of 3.3V; and when the PAD terminal potential is in the range of Vcc1-V.sub.thQP3 .about.Vcc1+V.sub.thQP3, the potential of the N well node NW is placed in the floating state.
The circuit using the two power sources of different potential levels as shown in FIG. 17 requires a more complex circuit structure than that using a power source of a single potential level. Further, during the output mode in the other two circuits shown in FIG. 16 and FIG. 18, and when the PAD terminal potential is at 3.3V, the potential at the N well node NW is placed in a floating state. For this reason, the parasitic diode in the driver PMOS transistor QP3 works as a coupling capacitor, and therefore, in particular, during the output mode, the potential of the N well node is affected by the change in the operating condition of the driver PMOS transistor QP3. Accordingly, the parasitic diode formed between the source connected to Vcc1 and the N well node NW of the driver PMOS transistor QP3 may sometimes be forward biased, which reduces the noise resistance and the latch-up resistance thereof. On the other hand, when the potential of the N well node NW remains high, the parasitic diode is reverse biased, which increases the threshold voltage V.sub.thQP3 due to a substrate biasing effect, to thereby reduce the current driving capability of the PMOS transistor QP3 and deteriorate the operation speed thereof.